Boundary Scan / JTAG (Joint Test Action Group)

Boundary Scan, also known as JTAG (Joint Test Action Group), is a technique used to test and debug chips without requiring physical access to their pins. It is based on the IEEE 1149.1–1990 standard, which defines a set of rules and protocols for chip communication. The core concept involves inserting a Boundary Scan Cell between each chip pin and its internal logic.

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Why Boundary Scan?

When working with chips from different vendors that use various protocols and are assembled on a PCB, a unified way to test them together becomes essential. Boundary Scan provides this solution.

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Purpose of Boundary Scan

1. Fault Testing: Identifying faults in the interconnections between chips on a PCB.
2. Internal Logic Access: Testing the internal logic of chips to verify functionality.
3. Controllability & Observability: Controlling and observing the I/O pins of chips.

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Components of JTAG

1. TAP (Test Access Port)

• Connects Chips to Tester: Allows external communication through JTAG signals.
• TAP FSM: A finite state machine managing test logic modes and operations.
• Five Pins:
  • TCK: Test Clock.
  • TMS: Test Mode Select.
  • TDI: Test Data Input.
  • TDO: Test Data Output.
  • TRST: Test Reset (optional).

2. TAP Controller

• A finite state machine (FSM) with 16 states.
• Manages read/write operations via TDI and TDO pins.

3. Registers

• Instruction Register (IR): Stores instructions specifying operational modes and target data registers.
• Data Registers (DR): Stores data for testing. Types include:
  • Boundary Scan Register (BSR): Observes and controls I/O pins.
  • Bypass Register (BR): Bypasses chips during testing.
  • ID Code Register: Stores chip ID information.
  • Device-Specific Registers: Unique to the chip.

4. Instruction Decoder

• Decodes instructions from IR to control chip operations.

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Boundary Scan Register (BSR)

• Purpose: Controls and observes I/O pins for testing.
• Operation: Managed via TAP controller for data transfer.
• Architecture: Boundary Scan Cells (BSCs) are arranged in a chain to cover all chip pins.

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JTAG FSM States

1. Test Logic Reset: Resets JTAG circuits.
2. Run-Test/Idle: Initializes test logic.
3. Select-DR/IR: Selects data or instruction registers.
4. Capture-DR/IR: Captures data in registers.
5. Shift-DR/IR: Serially shifts data in/out of registers.
6. Update-DR/IR: Updates data from registers to system logic.
7. Pause-DR/IR: Pauses data shifting temporarily.

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Boundary Scan Cell (BSC) Operations

1. Capture Mode: Captures test responses from inputs.
2. Shift Mode: Shifts data through the scan chain.
3. Update Mode: Transfers data to output flops.
4. Normal Mode: Acts as a transparent buffer connecting internal logic to I/O pins.

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JTAG Instructions

1. IDCODE: Retrieves the chip’s ID.
2. BYPASS: Bypasses the chip, reducing test time.
3. SAMPLE/PRELOAD: Captures or preloads pin values without interfering with logic.
4. EXTEST: Tests interconnections between chips.
5. INTEST: Tests internal chip functionality.
6. HIGHZ: Isolates chip output pins (high-impedance state).
7. CLAMP: Locks output pins to a specific value.

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Summary

Boundary Scan / JTAG simplifies testing and debugging of chips on PCBs by providing standardized methods to control and observe chip operations. Its versatility, including fault detection, functionality verification, and reduced test times, makes it indispensable for modern electronic systems. By leveraging JTAG, engineers can ensure robust and efficient testing processes.